SPI0=0, ACMP2=0, UART3=0, ACMP0=0, UART0=0, IIC1=0, UART1=0, EWM=0, ACMP1=0, UART2=0, IIC0=0, CMT=0, ACMP3=0, SPI1=0
System Clock Gating Control Register 5
| RESERVED | no description available |
| EWM | EWM Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| CMT | CMT Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| RESERVED | no description available |
| IIC0 | IIC0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| IIC1 | IIC1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| UART0 | UART0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| UART1 | UART1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| UART2 | UART2 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| UART3 | UART3 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| RESERVED | no description available |
| SPI0 | SPI0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| SPI1 | SPI1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| ACMP0 | ACMP0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| ACMP1 | ACMP1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| ACMP2 | ACMP2 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| ACMP3 | ACMP3 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| RESERVED | no description available |